The invention relates to a method of manufacturing a semiconductor device comprising semiconductor elements having semiconductor zones formed in a silicon wafer""s monocrystalline top layer situated on a buried insulating layer, in which method a first series of process steps is carried out, inter alia, process steps wherein the wafer is heated to a temperature above 700xc2x0 C., whereafter trenches are formed in the top layer which extend as far as the buried insulating layer and which do not intersect pn-junctions, which trenches are subsequently filled with an insulating material, after which a second series of process steps is finally carried out, wherein the semiconductor device is completed, in which second series of process steps the wafer does not exceed a temperature of 400xc2x0 C.
In this method, for the starting material use is made of a wafer of silicon having a monocrystalline top layer situated on a layer of an insulating material buried in the wafer, said layer of insulating material generally being a layer of silicon oxide. This wafer is provided with semiconductor elements, such as bipolar transistors or MOS transistors. In the first series of process steps, semiconductor zones are formed in the top layer of this SOI (Silicon-On-Insulator) wafer, which semiconductor zones are of the opposite conductivity type which respect to the top layer, and, thus, form pn-junctions with said top layer. Insulating regions of silicon oxide are also often formed in the top layer by local thermal oxidation of said top layer. It is additionally possible to form layers of polycrystalline silicon, silicon oxide or silicon nitride on the top layer. This can be achieved by deposition or, alternatively, by chemical conversion of the surface of the top layer. In this first series of process steps, which form the xe2x80x9cfront-endxe2x80x9d of the manufacturing process, the wafer is often heated to temperatures above 700xc2x0 C., for example, to activate implanted ions, form silicon oxide by thermal oxidation or deposit layers. After this first series of process steps, trenches are formed in the top layer, which are subsequently filled with an insulating material. These trenches can be used, for example, to electrically insulate the semiconductor elements with respect to each other. In the second series of process steps, wherein the semiconductor device is completed, and which forms the xe2x80x9cback-endxe2x80x9d of the manufacturing process, a metallization which may comprise one or more layers of metal patterns and layers of insulating material is formed on the wafer. As a result of this metallization, the semiconductor elements are connected to one another. Finally, in practice, a few insulating layers and an envelope are provided. During this second series of processes, the wafer is only heated to temperatures which do not exceed said 400xc2x0 C.
In U.S. Pat. No. 5,872,044, a description is given of a method of the type mentioned in the opening paragraph, wherein the trenches in the top layer are filled in two process steps. In the first step, the wall of the trenches is provided with a layer of silicon oxide by thermal oxidation. In the second step, the trench is further filled with polycrystalline silicon or silicon oxide.
As the trenches are not formed and subsequently filled until after said xe2x80x9cfrontendxe2x80x9d process steps have been carried out, it is achieved that the filled trenches are not subjected again to the high temperatures at which these process steps are often carried out. If the trenches were formed and filled prior to carrying out the xe2x80x9cfront-endxe2x80x9d processes, then mechanical stresses capable of causing undesirable crystal errors in the top layer would occur in the part of the top layer surrounded by the trenches due to heating of such filled trenches. The formation of said crystal errors is precluded because the trenches are not formed and subsequently filled until after the xe2x80x9cfront-endxe2x80x9d processes have been carried out.
As the semiconductor elements are formed in a SOI wafer, a good vertical insulation of the semiconductor elements is achieved. As a result, the known method described above seems to be very suitable for the manufacture of semiconductor devices comprising semiconductor elements which can suitably be used to process high-frequency signals. However, in the manufacture of semiconductor devices used to process signals having frequencies above 10 GHz, it has been found that the known, above-described method is unsatisfactory. In the case of semiconductor elements which can suitably be used to process signals having such high frequencies, the semiconductor zones must be small and shallow, and also the interspace between the semiconductor zones should be small. To preclude mutual differences between the transistors, these small and shallow semiconductor zones should additionally be equally large and equally deep everywhere, viewed over the wafer. A bipolar transistor which can suitably be used to process such signals must, for example, have an n-type emitter zone having lateral dimensions of approximately 400 nm and a depth of approximately 50 nm, which emitter zone is formed in a p-type base zone having a depth of 200 nm, the thickness of the base zone then being 150 nm. These zones can be formed, for example, in an n-type top layer having a thickness of approximately 800 nm. When the known method is used, it is practically impossible to manufacture such transistors having said small emitter and base zones. In particular, it has been found to be practically impossible to manufacture emitter zones having such a small depth.
It is an object of the invention to provide a method which can be carried out more readily than the known method and which, in addition, makes it possible to manufacture semiconductor elements which are suitable to process signals having frequencies above 10 GHz. The invention particularly aims at providing a method which can suitably be used to manufacture semiconductor zones having a very small depth of, for example, less than 50 nm.
To achieve this, the method is characterized in accordance with the invention in that the trenches are filled with an insulating material by means of a deposition process in which the wafer is not heated to a temperature above 500xc2x0 C.
In the above-described, known method, the walls of the trenches are provided with an approximately 50 nm thick layer of silicon oxide by thermal oxidation of the toplayer""s silicon adjoining these walls. To this end, the wafer must be heated to a temperature of 900xc2x0 C. for, for example, 30 minutes. Subsequently, the trenches are filled with polycrystalline silicon or silicon oxide. For this purpose, the wafer must be heated for several hours to a temperature of approximately 700xc2x0 C. It has been found that such temperature treatments impede the formation of the desired shallow semiconductor zones.
In the known method, the wall of the trenches is provided with a very dense layer of thermally formed silicon oxide which will very well passivate the xe2x80x9cdangling bondsxe2x80x9d present on the wall of the trenches. The invention is based on the recognition that this is not necessary. As the trenches do not intersect pn-junctions, the trenches can be directly filled with insulating material without their walls being provided with a layer of a thermal oxide first. It has been found that a good mutual insulation of the semiconductor elements can be achieved if the trenches are filled with an insulating material whose density is smaller than that of thermally formed silicon oxide. Such a lower-quality insulating material can be readily deposited at temperatures below 400xc2x0 C.
In a first example, the trenches are filled by depositing, in the trenches and next to the trenches, a layer of a synthetic resin on the wafer, whereafter windows are formed in this layer, which serve to make contact with the semiconductor elements situated under the layer. Preferably, said synthetic resin layer is a layer of benzocyclobutene (BCB). Such a layer can be provided by means of a customary spin-coating process. In this manner, the trenches are filled in a simple and inexpensive manner.
In a second example, the trenches are filled by depositing, in the trenches and next to the trenches, a silicon oxide layer on the wafer from a plasma generated in a vapor of silicon and oxygen-containing components. Said layer of silicon oxide is preferably deposited from a plasma generated in a vapor of silane and laughing gas. During the deposition of such a layer, the wafer does not reach temperatures above 400xc2x0 C. This method has the additional advantage that, apart from the semiconductor elements, passive elements, such as capacitors and coils, can be provided on the layer,. These passive elements are insulated from the underlying silicon wafer by the layer of silicon oxide deposited as described above.
Preferably, the deposited layer of silicon oxide is planarized by means of a chemical-mechanical polishing process. In such a process, which is carried out at room temperature, the wafer is not heated. In addition to the semiconductor elements, the metallization and said passive element can be readily formed on the layer thus planarized. Preferably, at the location of the passive elements, the insulating buried layer is exposed in the process step wherein the trenches are formed, prior to the deposition of the silicon oxide layer. The passive elements are thus provided on a layer of planarized silicon oxide which, at the location of these passive elements, is directly provided on the insulating buried layer. As a result of the absence of the doped top layer, these passive elements will exhibit a better high-frequency behavior than passive elements formed at locations where the top layer has not been removed. For example, coils will exhibit a higher quality factor.